1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a pipe latch control circuit of a semiconductor integrated circuit.
2. Related Art
In general, a synchronous memory has a pipe latch so as to input/output consecutive data. The pipe latch is a circuit that stores data provided from a memory cell and then sequentially outputs the stored data in synchronization with a clock.
If the number of pipe latches is increased, a waiting time required in outputting data is generally lengthened, and hence the data can be stably outputted. However, the area occupied by the pipe latches is broadened, and the waiting time required in outputting the data is increased. Therefore, it is not suitable to operate the memory at a high speed. On the contrary, if the number of pipe latches is decreased, the waiting time required in outputting data is shortened, but a timing margin required in outputting the data is not secured. Therefore, the reliability of the operation of the memory cannot be ensured.
FIG. 1 is a timing diagram of data outputted from a general pipe latch. As illustrated in FIG. 1, data is stored in a first pipe latch PIPE0 by a first read command RD1 after a predetermined time tA. The predetermined time tA is a time from when data is detected in a semiconductor memory cell and then stored in a pipe latch.
Since the data stored in the first pipe latch PIPE0 is not outputted, data is stored in a second pipe latch PIPE1 by a second read command RD2 after the predetermined time tA elapses from the application of the second read command RD2. Since the data stored in the first and second pipe latches PIPE0 and PIPE1 are not outputted, data is stored in a third pipe latch PIPE2 by a third read command RD3 after the predetermined time tA elapses from the application of the third read command RD3. The data DQ stored in the first pipe latch PIPE0 is outputted after a first CAS latency CL1.
Here, a CAS latency uses one period of an external clock signal as a unit time, and has time information from the time when a read command is applied to the time when data is outputted.
The output of the data stored in the first pipe latch PIPE0 is started after the first CAS latency CL1, and the output of the data is not completed until the predetermined time tA elapses after the application of a fourth read command RD4. Therefore, the reliability of the operation of the memory is not ensured.